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| Test synthesis in the microprocessor product development cycle;John M. Acken and Dhanendra D. Jani; Custom Integrated Circuits Conference, 1995.,Proceedings of the IEEE 1995. | Gopal Sundararajan | gopalak@okstate.edu
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| VHDL fault simulation for defect-oriented test and diagnosis of digital ICs ; European Design Automation Conference Proceedings ;1996 | Clark Shaver | clark.shaver@centrilift.com
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| Characterization and Testing of Physical Failures in MOS Logic Cirucs IEEE Design And Test; P. Banerjee and J. A. Abraham; August 1984 | Patrick Teague | patrick.teague@okstate.edu
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| Comparison of Aliasing Errors for Primitive and Non-Primitive Polynomials; T.W. Williams, C.W. Starke, W. Daehn and M. Gruetzner ;Proceedings of International Test Conference 1986 | khadija1988 | etudiante_english@hotmail.com
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| Implementing 1149.1 on CMOS Microprocessors; William C. Bruce, Michael G. Gallup, Grady Giles and Tom Munns ;Proceedings of International Test Conference 1991 | Justin | Remington
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| Random and Systematic Defect Analysis Using IDDQ Signature Analysis for Understanding Fails and Guiding Test Decisions; P. Nigh, A. Gattiker; Proceedings of International Test Conference 2004 | Kazunori Nishimura | kazunori.nishimura@okstate.edu
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| Beyond the Byzantine Generals: Unexpected Behavior and Bridging Fault Diagnosis; D. B. Lavo, T. Larrabee, and B. Chess, . Proceedings of the International Test Conference, 611-619, October 1996. | rehan ahmed | rehan.ahmed@okstate.edu
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| Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks; H. Konuk, F.J. Ferguson, and T. Larrabee. . In Proceedings of the Design Automation Conference, pages 345-351, 1995. | Brian Gordon | brian.gordon@okstate.edu
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| Explorations of Sequential ATPG Using Boolean Satisfiability.;H. Konuk, and T. Larrabee. In Proceedings of the 11th VLSI Test Symposium, pages 85-90, 1993. | Hrishikesh Bhadange | hrishikesh.bhadange@okstate.edu
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| Evidence for a Satisfiability Threshold for Random 3CNF Formulas.;T. Larrabee and Y. Tsuji. In Proceedings of the AAAI Symposium on AI and NP-Hard Problems, 1992. | Available
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| Test Pattern Generation for Realistic Bridge Faults in CMOS ICs, ;F.J. Ferguson, and T. Larrabee. . In Proceedings of the International Test Conference, pages 492-499, 1991. | pratibha | pratibha.kota@okstate.edu
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| The concurrent simulation of nearly identical digital networks; E. G. Ulrich and T. Baker; Proceedings of DAC 1973 | Sumanth Bathula | sumanth.bathula@okstate.edu
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| Test Pattern Generation Using Boolean Satisfiability;T. Larrabee.. In 1992. IEEE Transactions on Computer-Aided Design, pages 4-15, Jan, 1992.1 | Swetha Bezawada | swetha.bezawada@okstate.edu
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| Accurate modeling and simulation of bridging faults, J. M. Acken and S. D. Millman, Proc. Custom Integrated Circuits Conf., pp. 17.4.1-17.4.4, 1991. | Sunil Kumar Lakkakula | sunilkumar.lakkakula@okstate.edu
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| Fault model evolution for diagnosis: Accuracy vs precision, J. M. Acken and S. D. Millman, Proc. Custom Integrated Circuits Conf., 1992. | Wira Mulia | wira.mulia@okstate.edu
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| Diagnosing arbitrary defects in logic designs using single location at a time (SLAT), Huisman, L.M. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on On page(s): 91- 101, Volume: 23, Issue: 1, Jan. 2004 | Vaibhav Deshpande | vaibhav.deshpande@okstate.edu
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| Test line for the list | John M. Acken | John.M.Acken@okstate.edu
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